Delay-reduction technique for DWA algorithms

Chadi Jabbour; Hussein Fakhoury; Van Tam Nguyen; Patrick Loumeau

doi:10.1109/TCSII.2014.2335437

Delay-reduction technique for DWA algorithms

Chadi Jabbour
, Hussein Fakhoury
, Van Tam Nguyen
, Patrick Loumeau

CNRS
Telecom Paris
University of California, Berkeley

Résultats de recherche: Contribution à un journal › Article › Revue par des pairs

Résumé

This brief presents a delay-reduction technique for data weighted averaging (DWA) algorithms. The proposed technique is based on quantizing the shift pointer of the DWA circuit, which leads to a complexity reduction of the shuffler and, consequently, to a delay reduction as well. Synthesis results in a 65-nm CMOS process show that the proposed technique reduces DWA delay below 100 ps for a 5-bit delta-sigma modulator. The proposed technique reduces the DWA in-band tones that arise as well, particularly for low input amplitudes.

langue originale	Anglais
Numéro d'article	2335437
Pages (de - à)	733-737
Nombre de pages	5
journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	61
Numéro de publication	10
Les DOIs	https://doi.org/10.1109/TCSII.2014.2335437
état	Publié - 1 oct. 2014

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10.1109/TCSII.2014.2335437

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title = "Delay-reduction technique for DWA algorithms",

abstract = "This brief presents a delay-reduction technique for data weighted averaging (DWA) algorithms. The proposed technique is based on quantizing the shift pointer of the DWA circuit, which leads to a complexity reduction of the shuffler and, consequently, to a delay reduction as well. Synthesis results in a 65-nm CMOS process show that the proposed technique reduces DWA delay below 100 ps for a 5-bit delta-sigma modulator. The proposed technique reduces the DWA in-band tones that arise as well, particularly for low input amplitudes.",

keywords = "Analog-to-digital converter (ADC), Data weighted averaging (DWA), Delta-sigma (ΔΣ) modulator, Digital-to-analog converter (DAC) linearization",

author = "Chadi Jabbour and Hussein Fakhoury and Nguyen, \{Van Tam\} and Patrick Loumeau",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.",

year = "2014",

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doi = "10.1109/TCSII.2014.2335437",

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AU - Nguyen, Van Tam

AU - Loumeau, Patrick

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N2 - This brief presents a delay-reduction technique for data weighted averaging (DWA) algorithms. The proposed technique is based on quantizing the shift pointer of the DWA circuit, which leads to a complexity reduction of the shuffler and, consequently, to a delay reduction as well. Synthesis results in a 65-nm CMOS process show that the proposed technique reduces DWA delay below 100 ps for a 5-bit delta-sigma modulator. The proposed technique reduces the DWA in-band tones that arise as well, particularly for low input amplitudes.

AB - This brief presents a delay-reduction technique for data weighted averaging (DWA) algorithms. The proposed technique is based on quantizing the shift pointer of the DWA circuit, which leads to a complexity reduction of the shuffler and, consequently, to a delay reduction as well. Synthesis results in a 65-nm CMOS process show that the proposed technique reduces DWA delay below 100 ps for a 5-bit delta-sigma modulator. The proposed technique reduces the DWA in-band tones that arise as well, particularly for low input amplitudes.

KW - Analog-to-digital converter (ADC)

KW - Data weighted averaging (DWA)

KW - Delta-sigma (ΔΣ) modulator

KW - Digital-to-analog converter (DAC) linearization

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JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 10

M1 - 2335437

ER -

Delay-reduction technique for DWA algorithms

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