TY - GEN
T1 - Design and hardware implementation of digital channel selection decimating filter for multistandard receiver
AU - Grati, K.
AU - Ghazel, A.
AU - Naviner, L.
PY - 2005/12/1
Y1 - 2005/12/1
N2 - This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection decimating filter for multistandard receiver. Authors propose an optimized multistage decimation filter for a frontend composed by an Homodyne wide-band RF receiver and Sigma-Delta modulator. Design flow of hardware architecture is presented through the choice of filter structure and architecture. Several results are given to evaluate performances and complexity of designed FPGA-based implementation that can support GSM, DECT and UMTS standard.
AB - This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection decimating filter for multistandard receiver. Authors propose an optimized multistage decimation filter for a frontend composed by an Homodyne wide-band RF receiver and Sigma-Delta modulator. Design flow of hardware architecture is presented through the choice of filter structure and architecture. Several results are given to evaluate performances and complexity of designed FPGA-based implementation that can support GSM, DECT and UMTS standard.
UR - https://www.scopus.com/pages/publications/56749184088
U2 - 10.1109/ICECS.2005.4633452
DO - 10.1109/ICECS.2005.4633452
M3 - Conference contribution
AN - SCOPUS:56749184088
SN - 9789972611001
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
BT - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
T2 - 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005
Y2 - 11 December 2005 through 14 December 2005
ER -