Design and hardware implementation of digital channel selection processor for radio receiver

Khaled Grati; Adel Ghazel; Lirida Naviner

Design and hardware implementation of digital channel selection processor for radio receiver

Khaled Grati
, Adel Ghazel
, Lirida Naviner

University of Carthage, Ecole Supérieure des Communications de Tunis
Telecom Paris

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

Résumé

This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection filtering processor for Radio receiver. For an homodyne wide-band RF receiver and Sigma-Delta modulator, two filtering cascade structures composed of 5 stages Comb filter, FIR half-band filter and selector filter are compared. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators. Experimental results are given to evaluate performances and complexity of designed FPGA-based implementation.

langue originale	Anglais
titre	Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology
Pages	152-156
Nombre de pages	5
état	Publié - 1 déc. 2004
Evénement	Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004 - Rome, Italie Durée: 18 déc. 2004 → 21 déc. 2004

Série de publications

Nom	Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004

Une conférence

Une conférence	Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004
Pays/Territoire	Italie
La ville	Rome
période	18/12/04 → 21/12/04

Contient cette citation

Grati, K., Ghazel, A., & Naviner, L. (2004). Design and hardware implementation of digital channel selection processor for radio receiver. Dans Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology (p. 152-156). (Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004).

Grati, Khaled ; Ghazel, Adel ; Naviner, Lirida. / Design and hardware implementation of digital channel selection processor for radio receiver. Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology. 2004. p. 152-156 (Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004).

@inproceedings{eb5e73ff973145cd96a713a03ecae655,

title = "Design and hardware implementation of digital channel selection processor for radio receiver",

abstract = "This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection filtering processor for Radio receiver. For an homodyne wide-band RF receiver and Sigma-Delta modulator, two filtering cascade structures composed of 5 stages Comb filter, FIR half-band filter and selector filter are compared. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators. Experimental results are given to evaluate performances and complexity of designed FPGA-based implementation.",

keywords = "Digital decimating filter, FPGA implementation, Low-power design",

author = "Khaled Grati and Adel Ghazel and Lirida Naviner",

year = "2004",

month = dec,

day = "1",

language = "English",

isbn = "0780386892",

series = "Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004",

pages = "152--156",

booktitle = "Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology",

note = "Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004 ; Conference date: 18-12-2004 Through 21-12-2004",

}

Grati, K, Ghazel, A & Naviner, L 2004, Design and hardware implementation of digital channel selection processor for radio receiver. Dans Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology. Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004, p. 152-156, Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004, Rome, Italie, 18/12/04.

Design and hardware implementation of digital channel selection processor for radio receiver. / Grati, Khaled; Ghazel, Adel; Naviner, Lirida.
Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology. 2004. p. 152-156 (Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

TY - GEN

T1 - Design and hardware implementation of digital channel selection processor for radio receiver

AU - Grati, Khaled

AU - Ghazel, Adel

AU - Naviner, Lirida

PY - 2004/12/1

Y1 - 2004/12/1

N2 - This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection filtering processor for Radio receiver. For an homodyne wide-band RF receiver and Sigma-Delta modulator, two filtering cascade structures composed of 5 stages Comb filter, FIR half-band filter and selector filter are compared. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators. Experimental results are given to evaluate performances and complexity of designed FPGA-based implementation.

AB - This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection filtering processor for Radio receiver. For an homodyne wide-band RF receiver and Sigma-Delta modulator, two filtering cascade structures composed of 5 stages Comb filter, FIR half-band filter and selector filter are compared. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators. Experimental results are given to evaluate performances and complexity of designed FPGA-based implementation.

KW - Digital decimating filter

KW - FPGA implementation

KW - Low-power design

M3 - Conference contribution

AN - SCOPUS:21544458055

SN - 0780386892

T3 - Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004

SP - 152

EP - 156

BT - Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology

T2 - Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004

Y2 - 18 December 2004 through 21 December 2004

ER -

Design and hardware implementation of digital channel selection processor for radio receiver

Résumé

Série de publications

Une conférence

Empreinte digitale

Contient cette citation