TY - GEN
T1 - Design and implementation of MPSoC single chip with butterfly network
AU - Hamwi, Khawla
AU - Hammami, Omar
PY - 2010/12/1
Y1 - 2010/12/1
N2 - Multiprocessor System on Chip (MPSoC) are increasingly considered as the post promising solution for complex embedded applications. The most significant MPSoC design challenge comes from interconnect infrastructure. Network-on-Chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges. It has been shown that infrastructure topology; routing and switching schemes have great effects on overall interconnect performance under different synthesis and real life traffic patterns. In this paper, we report the design and single FPGA chip implementation of an 8-node butterfly network based on MPSoC. We analyze the performance of this MPSoC on a radix-2 Fast Fourier Transform whereas the FFT algorithm is parallel programmed and it uses our NoC as a communication environment. Additionally, an exploration is done in two dimensions the number of processors used in parallelism process and the input dataset size of the FFT.
AB - Multiprocessor System on Chip (MPSoC) are increasingly considered as the post promising solution for complex embedded applications. The most significant MPSoC design challenge comes from interconnect infrastructure. Network-on-Chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges. It has been shown that infrastructure topology; routing and switching schemes have great effects on overall interconnect performance under different synthesis and real life traffic patterns. In this paper, we report the design and single FPGA chip implementation of an 8-node butterfly network based on MPSoC. We analyze the performance of this MPSoC on a radix-2 Fast Fourier Transform whereas the FFT algorithm is parallel programmed and it uses our NoC as a communication environment. Additionally, an exploration is done in two dimensions the number of processors used in parallelism process and the input dataset size of the FFT.
KW - Butterfly topology
KW - Fast fourier transform
KW - Multi-processor system-on-chip
KW - Network-on-chip
UR - https://www.scopus.com/pages/publications/78650932893
U2 - 10.1109/VLSISOC.2010.5642607
DO - 10.1109/VLSISOC.2010.5642607
M3 - Conference contribution
AN - SCOPUS:78650932893
SN - 9781424464708
T3 - Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
SP - 143
EP - 148
BT - Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
T2 - 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
Y2 - 27 September 2010 through 29 September 2010
ER -