Digital excess loop delay compensation for high speed delta-sigma modulators

C. Jabbour; V. T. Nguyen; V. Srini; S. Aggarwal

doi:10.1049/el.2015.0949

Digital excess loop delay compensation for high speed delta-sigma modulators

C. Jabbour
, V. T. Nguyen
, V. Srini
, S. Aggarwal

Nokia Technology
University of California, Berkeley

Résultats de recherche: Contribution à un journal › Article › Revue par des pairs

2 Citations (Scopus)

Résumé

A digital excess loop delay (ELD) compensation suited for high speed delta-sigma modulators is presented. Its operation is based on computing the digital outputs for all the possible values of the ELD compensation feedback and performing the selection in the digital domain. The proposed technique also uses a novel comparator sharing approach which minimises the number of comparators needed in the quantiser.

langue originale	Anglais
Pages (de - à)	1155-1157
Nombre de pages	3
journal	Electronics Letters
Volume	51
Numéro de publication	15
Les DOIs	https://doi.org/10.1049/el.2015.0949
état	Publié - 23 juil. 2015
Modification externe	Oui

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10.1049/el.2015.0949

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@article{711b6352e74f4098bf6a3f779469fca0,

title = "Digital excess loop delay compensation for high speed delta-sigma modulators",

abstract = "A digital excess loop delay (ELD) compensation suited for high speed delta-sigma modulators is presented. Its operation is based on computing the digital outputs for all the possible values of the ELD compensation feedback and performing the selection in the digital domain. The proposed technique also uses a novel comparator sharing approach which minimises the number of comparators needed in the quantiser.",

author = "C. Jabbour and Nguyen, \{V. T.\} and V. Srini and S. Aggarwal",

note = "Publisher Copyright: {\textcopyright} The Institution of Engineering and Technology 2015.",

year = "2015",

month = jul,

day = "23",

doi = "10.1049/el.2015.0949",

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journal = "Electronics Letters",

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TY - JOUR

T1 - Digital excess loop delay compensation for high speed delta-sigma modulators

AU - Jabbour, C.

AU - Nguyen, V. T.

AU - Srini, V.

AU - Aggarwal, S.

PY - 2015/7/23

Y1 - 2015/7/23

N2 - A digital excess loop delay (ELD) compensation suited for high speed delta-sigma modulators is presented. Its operation is based on computing the digital outputs for all the possible values of the ELD compensation feedback and performing the selection in the digital domain. The proposed technique also uses a novel comparator sharing approach which minimises the number of comparators needed in the quantiser.

AB - A digital excess loop delay (ELD) compensation suited for high speed delta-sigma modulators is presented. Its operation is based on computing the digital outputs for all the possible values of the ELD compensation feedback and performing the selection in the digital domain. The proposed technique also uses a novel comparator sharing approach which minimises the number of comparators needed in the quantiser.

U2 - 10.1049/el.2015.0949

DO - 10.1049/el.2015.0949

M3 - Article

AN - SCOPUS:84937569858

SN - 0013-5194

VL - 51

SP - 1155

EP - 1157

JO - Electronics Letters

JF - Electronics Letters

IS - 15

ER -

Digital excess loop delay compensation for high speed delta-sigma modulators

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