Efficient computation of combinational circuits reliability based on probabilistic transfer matrix

Lirida Naviner; Kaikai Liu; Hao Cai; Jean François Naviner

doi:10.1109/ICICDT.2014.6838588

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix

Lirida Naviner
, Kaikai Liu
, Hao Cai
, Jean François Naviner

Institut Mines-Télécom

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

Résumé

The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.

langue originale	Anglais
titre	ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology
Editeur	IEEE Computer Society
ISBN (imprimé)	9781479921539
Les DOIs	https://doi.org/10.1109/ICICDT.2014.6838588
état	Publié - 1 janv. 2014
Modification externe	Oui
Evénement	2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014 - Austin, TX, États-Unis Durée: 28 mai 2014 → 30 mai 2014

Série de publications

Nom	ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

Une conférence

Une conférence	2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014
Pays/Territoire	États-Unis
La ville	Austin, TX
période	28/05/14 → 30/05/14

Accès au document

10.1109/ICICDT.2014.6838588

Contient cette citation

Naviner, L., Liu, K., Cai, H., & Naviner, J. F. (2014). Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. Dans ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology Article 6838588 (ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology). IEEE Computer Society. https://doi.org/10.1109/ICICDT.2014.6838588

@inproceedings{a349edfccfdc4a5b870ea8dfb7d11a41,

title = "Efficient computation of combinational circuits reliability based on probabilistic transfer matrix",

abstract = "The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.",

author = "Lirida Naviner and Kaikai Liu and Hao Cai and Naviner, \{Jean Fran{\c c}ois\}",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/ICICDT.2014.6838588",

language = "English",

isbn = "9781479921539",

series = "ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology",

publisher = "IEEE Computer Society",

booktitle = "ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology",

note = "2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014 ; Conference date: 28-05-2014 Through 30-05-2014",

}

Naviner, L, Liu, K, Cai, H & Naviner, JF 2014, Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. Dans ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology., 6838588, ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology, IEEE Computer Society, 2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014, Austin, TX, États-Unis, 28/05/14. https://doi.org/10.1109/ICICDT.2014.6838588

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. / Naviner, Lirida; Liu, Kaikai; Cai, Hao et al.
ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology. IEEE Computer Society, 2014. 6838588 (ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

TY - GEN

T1 - Efficient computation of combinational circuits reliability based on probabilistic transfer matrix

AU - Naviner, Lirida

AU - Liu, Kaikai

AU - Cai, Hao

AU - Naviner, Jean François

PY - 2014/1/1

Y1 - 2014/1/1

N2 - The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.

AB - The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.

U2 - 10.1109/ICICDT.2014.6838588

DO - 10.1109/ICICDT.2014.6838588

M3 - Conference contribution

AN - SCOPUS:84904205360

SN - 9781479921539

T3 - ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

BT - ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

PB - IEEE Computer Society

T2 - 2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014

Y2 - 28 May 2014 through 30 May 2014

ER -

Naviner L, Liu K, Cai H, Naviner JF. Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. Dans ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology. IEEE Computer Society. 2014. 6838588. (ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology). doi: 10.1109/ICICDT.2014.6838588

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix

Résumé

Série de publications

Une conférence

Accès au document

Empreinte digitale

Contient cette citation