TY - GEN
T1 - Efficient computation of logic circuits reliability based on probabilistic transfer matrix
AU - Naviner, Lirida A.B.
AU - De Vasconcelos, Maí C.R.
AU - Franco, Denis T.
AU - Naviner, Jean François
PY - 2008/9/10
Y1 - 2008/9/10
N2 - The development of fault tolerance techniques to enhance systems dependability is becoming an unavoidable task as IC industry enters in the nanoscale era. However, before consider the fault tolerant design, an accurate method of reliability evaluation is necessary. The knowledge of the natural error masking capabilities of a given circuit will be essential to handle design tradeoffs in the conception stage. This paper is intended to deal with improvements in the reliability computation of logic circuits using the Probabilistic Transfer Matrix (PTM) approach. We propose an algorithm that reduces memory requirements and can improve run-time performances in the most significant stage of the PTM algorithm, keeping the same accurate reliability analysis.
AB - The development of fault tolerance techniques to enhance systems dependability is becoming an unavoidable task as IC industry enters in the nanoscale era. However, before consider the fault tolerant design, an accurate method of reliability evaluation is necessary. The knowledge of the natural error masking capabilities of a given circuit will be essential to handle design tradeoffs in the conception stage. This paper is intended to deal with improvements in the reliability computation of logic circuits using the Probabilistic Transfer Matrix (PTM) approach. We propose an algorithm that reduces memory requirements and can improve run-time performances in the most significant stage of the PTM algorithm, keeping the same accurate reliability analysis.
U2 - 10.1109/DTIS.2008.4540217
DO - 10.1109/DTIS.2008.4540217
M3 - Conference contribution
AN - SCOPUS:51049121623
SN - 9781424415779
T3 - International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08
BT - International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08
T2 - nternational Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08
Y2 - 25 March 2008 through 27 March 2008
ER -