Efficient implementation for high accuracy DCT processor based on FPGA

This paper presents a highly parallel high precision implementation for two-dimensional discrete cosine transform processor. The architecture is based on distributed arithmetic to reduce the hardware amount and enhance the speed performance. The system has been developed in order to be synthesized on a re-configurable circuit. Complete use of the logic cell's capability is obtained with various architectural optimizations. These optimizations include pseudo multiplexing, special encoding and resource sharing for multiplications, additions and accumulations of partial inner products. 11 bits input pixels are processed, generating 14 bits output coefficients. System is built on a Flex10k circuit of Altera, works at 36 MHz circuit, and guarantees real-time processing for 18 MHz input pixel rate.