Embedded processors optimization with hardware in the loop

K. Ghali; O. Hammami

doi:10.1109/ISIE.2004.1571868

Embedded processors optimization with hardware in the loop

K. Ghali
, O. Hammami

IEEE

Résultats de recherche: Contribution à une conférence › Papier › Revue par des pairs

Résumé

The design of an embedded microprocessor for a given workload is a tremendous task by itself due to the numerous parameters involved and the ranges of their possible values. If power consumption and area are also to be considered then the problem is even more complicated and requires a suitable framework and methodology for exploring the vast multidimensional space for such a problem. In this paper we propose such a framework based onl direct execution on FPGA boards.

langue originale	Anglais
Pages	561-564
Nombre de pages	4
Les DOIs	https://doi.org/10.1109/ISIE.2004.1571868
état	Publié - 1 déc. 2004
Evénement	2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE - Durée: 4 mai 2004 → 7 mai 2004

Une conférence

Une conférence	2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE
période	4/05/04 → 7/05/04

Accès au document

10.1109/ISIE.2004.1571868

Contient cette citation

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title = "Embedded processors optimization with hardware in the loop",

abstract = "The design of an embedded microprocessor for a given workload is a tremendous task by itself due to the numerous parameters involved and the ranges of their possible values. If power consumption and area are also to be considered then the problem is even more complicated and requires a suitable framework and methodology for exploring the vast multidimensional space for such a problem. In this paper we propose such a framework based onl direct execution on FPGA boards.",

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AB - The design of an embedded microprocessor for a given workload is a tremendous task by itself due to the numerous parameters involved and the ranges of their possible values. If power consumption and area are also to be considered then the problem is even more complicated and requires a suitable framework and methodology for exploring the vast multidimensional space for such a problem. In this paper we propose such a framework based onl direct execution on FPGA boards.

KW - Embedded

KW - FPGA

KW - Processor

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DO - 10.1109/ISIE.2004.1571868

M3 - Paper

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Y2 - 4 May 2004 through 7 May 2004

ER -

Embedded processors optimization with hardware in the loop

Résumé

Une conférence

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Empreinte digitale

Contient cette citation