Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions

Han Le Duc; Chadi Jabbour; Patricia Desgreys; Van Tam Nguyen

doi:10.1109/ICECS.2016.7841191

Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions

Han Le Duc
, Chadi Jabbour
, Patricia Desgreys
, Van Tam Nguyen

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

Résumé

Time interleaving (TI) is one of the best approaches to relax the speed-power trade-off of analog-to-digital converters (ADC). However, channel mismatches especially timing can limit the resolution of TIADC if they are not addressed properly. To achieve an efficient calibration for these errors, the most difficult task is the error estimation in the digital domain. The correction is less problematic and can be done either in digital domain or in the analog domain. Two big families of estimation techniques are commonly employed: the free-band estimation and the cross-correlation estimation. This paper reviews and analyses these estimation techniques and highlights their limitations. It also presents solutions to overcome these limitations.

langue originale	Anglais
titre	2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
Editeur	Institute of Electrical and Electronics Engineers Inc.
Pages	297-300
Nombre de pages	4
ISBN (Electronique)	9781509061136
Les DOIs	https://doi.org/10.1109/ICECS.2016.7841191
état	Publié - 1 janv. 2016
Modification externe	Oui
Evénement	23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016 - Monte Carlo, Monaco Durée: 11 déc. 2016 → 14 déc. 2016

Série de publications

Nom	2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016

Une conférence

Une conférence	23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
Pays/Territoire	Monaco
La ville	Monte Carlo
période	11/12/16 → 14/12/16

Accès au document

10.1109/ICECS.2016.7841191

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Contient cette citation

Le Duc, H., Jabbour, C., Desgreys, P., & Nguyen, V. T. (2016). Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions. Dans 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016 (p. 297-300). Article 7841191 (2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2016.7841191

Le Duc, Han ; Jabbour, Chadi ; Desgreys, Patricia et al. / Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters : Limitations and solutions. 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 297-300 (2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016).

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title = "Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions",

abstract = "Time interleaving (TI) is one of the best approaches to relax the speed-power trade-off of analog-to-digital converters (ADC). However, channel mismatches especially timing can limit the resolution of TIADC if they are not addressed properly. To achieve an efficient calibration for these errors, the most difficult task is the error estimation in the digital domain. The correction is less problematic and can be done either in digital domain or in the analog domain. Two big families of estimation techniques are commonly employed: the free-band estimation and the cross-correlation estimation. This paper reviews and analyses these estimation techniques and highlights their limitations. It also presents solutions to overcome these limitations.",

author = "\{Le Duc\}, Han and Chadi Jabbour and Patricia Desgreys and Nguyen, \{Van Tam\}",

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Le Duc, H, Jabbour, C , Desgreys, P & Nguyen, VT 2016, Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions. Dans 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016., 7841191, 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Institute of Electrical and Electronics Engineers Inc., p. 297-300, 23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, 11/12/16. https://doi.org/10.1109/ICECS.2016.7841191

Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions. / Le Duc, Han; Jabbour, Chadi ; Desgreys, Patricia et al.
2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 297-300 7841191 (2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

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N2 - Time interleaving (TI) is one of the best approaches to relax the speed-power trade-off of analog-to-digital converters (ADC). However, channel mismatches especially timing can limit the resolution of TIADC if they are not addressed properly. To achieve an efficient calibration for these errors, the most difficult task is the error estimation in the digital domain. The correction is less problematic and can be done either in digital domain or in the analog domain. Two big families of estimation techniques are commonly employed: the free-band estimation and the cross-correlation estimation. This paper reviews and analyses these estimation techniques and highlights their limitations. It also presents solutions to overcome these limitations.

AB - Time interleaving (TI) is one of the best approaches to relax the speed-power trade-off of analog-to-digital converters (ADC). However, channel mismatches especially timing can limit the resolution of TIADC if they are not addressed properly. To achieve an efficient calibration for these errors, the most difficult task is the error estimation in the digital domain. The correction is less problematic and can be done either in digital domain or in the analog domain. Two big families of estimation techniques are commonly employed: the free-band estimation and the cross-correlation estimation. This paper reviews and analyses these estimation techniques and highlights their limitations. It also presents solutions to overcome these limitations.

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Le Duc H, Jabbour C , Desgreys P, Nguyen VT. Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions. Dans 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 297-300. 7841191. (2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016). doi: 10.1109/ICECS.2016.7841191

Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions

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