TY - GEN
T1 - Evolution of SI circuit performances with technological advances
AU - Desgreys, Patricia
AU - Loumeau, Patrick
PY - 2001/12/1
Y1 - 2001/12/1
N2 - This paper shows how switched current circuits take advantage of technological advances. The tendency is towards lower grid length and lower threshold voltage. The first developed point show consequences on static performances : with lower threshold voltage, power supply decreases but input signal swing also decreases ; with lower grid length, the occupied die area falls. The second point concerns SI circuits accuracy. With the significant fall of the minimum size of a transistor, an interesting evolution occurs. The charge injection problem has proven to be serious in switched-current systems. But, with recent technologies, we can show that the error due to charge injection is lower than thermal noise contribution. In future, it isn't worth to use sophisticated architectures to obtain good accuracy. Thus, SI circuits gain in simplicity and robustness. The last point offers a comparison of figure-of-merit reachable with 0.8μm, 0.6μm and 0.35μm CMOS standard processes.
AB - This paper shows how switched current circuits take advantage of technological advances. The tendency is towards lower grid length and lower threshold voltage. The first developed point show consequences on static performances : with lower threshold voltage, power supply decreases but input signal swing also decreases ; with lower grid length, the occupied die area falls. The second point concerns SI circuits accuracy. With the significant fall of the minimum size of a transistor, an interesting evolution occurs. The charge injection problem has proven to be serious in switched-current systems. But, with recent technologies, we can show that the error due to charge injection is lower than thermal noise contribution. In future, it isn't worth to use sophisticated architectures to obtain good accuracy. Thus, SI circuits gain in simplicity and robustness. The last point offers a comparison of figure-of-merit reachable with 0.8μm, 0.6μm and 0.35μm CMOS standard processes.
M3 - Conference contribution
AN - SCOPUS:38949128869
SN - 0780370570
SN - 9780780370579
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 305
EP - 308
BT - ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
T2 - 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Y2 - 2 September 2001 through 5 September 2001
ER -