Exploiting Timing-Power Causality for Post-Route Metric Prediction via Hierarchical Learning

Recently, Machine Learning (ML) methods have demonstrated that accurate post-route metric prediction can accelerate design space exploration by eliminating time consuming place and route (PnR) iterations. However, there has been limited effort in exploring the capabilities of ML to leverage hierarchical predictions in performance estimation. We propose a hierarchical Graph Neural Network (GNN) architecture that exploits the fundamental causal relationship between timing and power consumption in digital circuits. Unlike existing approaches that treat these metrics independently, our two stage model first predicts timing characteristics, then leverages these predictions to enhance power estimation accuracy. Trained and evaluated on 20 designs ranging from 1K to 150k gates in SkyWater 130nm technology, our approach achieves 7.3% mean absolute percentage error (MAPE) for timing and 4.32% for power predictions. The hierarchical structure enables a significant speedup compared to commercial PnR tools while maintaining prediction fidelity, allowing designers to explore design variants in an efficient manner.