FPGA design of an open-loop true random number generator

This paper presents the design methodology of a metastability-based True Random Number Generator (TRNG) on a Xilinx FPGA. As its structure is based on an open-loop delay chain, it provides both high throughput and security against physical attacks since it is not sensitive to coupling attacks as for oscillator-based TRNG. The proposed architecture, implemented in a Virtex-5 XC5VLX50T, uses 4% of the available resources and generates random bits at a 20 Mbps rate. This work gives a detailed description of the design methodology, more specifically the placement, routing and timing analysis of the TRNG structure. Also, the randomness quality of this TRNG has been validated using AIS-31 and NIST statistical tests.