Heterogeneous stacking of 3D MPSoC architecture: Physical implementation analysis and performance evaluation

3D integration is one of the feasible technologies for producing advanced computing architecture to support ever-increasing demand of higher performance computing especially in mobile devices. The emerging trend of multiprocessor architecture has made Network on Chip (NoC) architecture the best solution for future manycore architecture devices. In this work, we explore the implementation of heterogeneous 3D Multiprocessor System on Chip (MPSoC) stacking architecture and evaluate its performance in terms of timing and power consumption compared with its 2D counterpart. The proposed heterogeneous 3D MPSoC implementation approach is considered to be the best solution for the time being as there are no 3D-aware EDA tools available in the markets that capable of performing 3D optimization as in 2D EDA tools. We also perform physical implementation analysis on the clock tree structure between 2D and 3D architecture and examine the impact of using 2D EDA tools for designing 3D architecture. The implementation is based on industry-specific Tezzaron 3D IC technology and the evaluation is based on the GDSII results from physical design implementations.