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Leveraging Interaction between Memory Footprint and Parallelism Degree for efficient GPU Portings

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  • Telecom Sudparis
  • CEA/UVSQ/CNRS

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Résumé

Porting large HPC applications entirely on a Graphics Processing Unit (GPU) can be challenging. Some code portions are indeed unsuitable for GPU porting. Therefore, selecting the most profitable code parts for GPU porting is crucial. Many profiling tools address this issue, but their overhead is non-negligible for large HPC test cases. Moreover, the extracted code parts might not be the best candidates for any input set size. We present an approach that extrapolates the behavior of pre-selected code parts from different input set size runs on a target GPU. This enables developers to evaluate the application's parallelism potential and memory footprint prior to GPU porting. We applied our approach to several HPC mini-applications and evaluated the extrapolations through a comparison to the existing GPU versions, as ground truth, on different vendors' GPUs. Our results provide input set sizes of magnitude leading to GPU memory saturation and recommend which pre-selected code parts should be further studied for GPU porting.

langue originaleAnglais
titreProceedings - 2025 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2025
EditeurInstitute of Electrical and Electronics Engineers Inc.
Pages857-865
Nombre de pages9
ISBN (Electronique)9798331526436
Les DOIs
étatPublié - 1 janv. 2025
Evénement2025 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2025 - Milan, Italie
Durée: 3 juin 20257 juin 2025

Série de publications

NomProceedings - 2025 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2025

Une conférence

Une conférence2025 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2025
Pays/TerritoireItalie
La villeMilan
période3/06/257/06/25

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