TY - GEN
T1 - Max-log demapper architecture design for DVB-T2 rotated QAM constellations
AU - Yang, Jianxiao
AU - Li, Meng
AU - Li, Min
AU - Nour, Charbel Abdel
AU - Douillard, Catherine
AU - Geller, Benoit
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/12/2
Y1 - 2015/12/2
N2 - Rotated and cyclic-Q delayed (RCQD) quadrature amplitude modulation (QAM) improve DVB-T2 system performance over highly time-frequency selective channels. However, when compared with conventional QAM demapper, the RCQD demapper requires a higher computational complexity. In this paper, a complexity-reduced max-log demapper is derived and implemented over a FPGA platform. The proposed demapper allows to find the maximum likelihood (ML) point with a search spanning only √M signal constellation points and guarantees to obtain the same log-likelihood ratio (LLR) metrics as the optimum max-log soft decision demapper while spanning at most 2√M signal constellation points. The optimized hardware implementation introduces only a slight performance loss compared to the floating-point full complexity max-log performance.
AB - Rotated and cyclic-Q delayed (RCQD) quadrature amplitude modulation (QAM) improve DVB-T2 system performance over highly time-frequency selective channels. However, when compared with conventional QAM demapper, the RCQD demapper requires a higher computational complexity. In this paper, a complexity-reduced max-log demapper is derived and implemented over a FPGA platform. The proposed demapper allows to find the maximum likelihood (ML) point with a search spanning only √M signal constellation points and guarantees to obtain the same log-likelihood ratio (LLR) metrics as the optimum max-log soft decision demapper while spanning at most 2√M signal constellation points. The optimized hardware implementation introduces only a slight performance loss compared to the floating-point full complexity max-log performance.
KW - DVB-T2
KW - Log-Likelihood Ratio (LLR)
KW - Max-Log Demapper
KW - Rotated and Cyclic Q Delayed (RCQD) Constellations
U2 - 10.1109/SiPS.2015.7344998
DO - 10.1109/SiPS.2015.7344998
M3 - Conference contribution
AN - SCOPUS:84958190853
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
BT - Electronic Proceedings of the 2015 IEEE International Workshop on Signal Processing Systems, SiPS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Workshop on Signal Processing Systems, SiPS 2015
Y2 - 14 October 2015 through 16 October 2015
ER -