Mechanisms of threshold voltage shift in polymorphous and microcrystalline silicon bottom gate thin-film transistors

In this paper, we have studied the stability of polymorphous silicon (pm-Si:H) and (c-Si:) bottom gate thin-film transistors (TFTs) by combining degradation and relaxation experiments under various stress conditions. We report on polymorphous silicon (pm-Si:H) TFTs with =1 after 10 h of stress and TFTs with superior stability, which show a δ V _{\rm TH} of only 0.05 V under stress conditions similar to those encountered in active-matrix operation regime and $VD=10. Relaxation studies show that the quality of the interface between silicon nitride and pm-Si:H (or controls the stability at short stress times. Interestingly, the deposition conditions of the semiconductor layer seem to modify the quality of the a-SiN:H and thus the stability of the interface.