MHYNESYS II: Multi-stage hybrid Network on chip synthesis for Next Generation 3D IC Manycore

Next generation manycore will contain hundreds of processors and the main challenge to be solved will be the network on chip (NOC) bottleneck of these systems which restricts scalability. At the crossroad of multiple technological trends, 3D IC, optical network on chip (ONOC) and further downscale in traditional 2D semiconductor, this paper proposes hybrid NOC synthesis as a way to exploit respective technological advances as they emerge. Rather than consider design as a static view of design parameters, hybrid Network on Chip (NoC) synthesis generates a hybrid NOC under the assumption of 3D and optical network while capturing latest technological advances exposed by components libraries and EDA tools. This will be explained through MHYNESYS II, a Multi-stages Hybrid Optical-electronics Network on Chip Synthesis for Next Generation 3D IC Manycore.