MMIC impedance matching system

R. N. De Lima; B. Huyart; E. Bergeault; L. Jallet

doi:10.1049/el:20000955

MMIC impedance matching system

R. N. De Lima
, B. Huyart
, E. Bergeault
, L. Jallet

CNRS
Federal University of Bahia

Résultats de recherche: Contribution à un journal › Article › Revue par des pairs

Résumé

An MMIC impedance system incorporating an on-chip load reflection-coefficient measurement system is presented. The system is capable of correcting load mismatches of up to 5:1 better than 2:1 VSWR with an insertion loss between 3.5-5.8 dB. A SiGe power amplifier, with reactive tee input-output matching circuits, was simulated using HP-advanced design system and load-pull technique. The simulation showed that a load mismatch of VSWR 3:1 can produce 10 dB attenuation in output power, relative to the power that would be the power that would be generated if there were no load mismatch.

langue originale	Anglais
Pages (de - à)	1393-1394
Nombre de pages	2
journal	Electronics Letters
Volume	36
Numéro de publication	16
Les DOIs	https://doi.org/10.1049/el:20000955
état	Publié - 3 août 2000

Accès au document

10.1049/el:20000955

Contient cette citation

@article{adb109f8f9194bf2a74c237bafd56c05,

title = "MMIC impedance matching system",

abstract = "An MMIC impedance system incorporating an on-chip load reflection-coefficient measurement system is presented. The system is capable of correcting load mismatches of up to 5:1 better than 2:1 VSWR with an insertion loss between 3.5-5.8 dB. A SiGe power amplifier, with reactive tee input-output matching circuits, was simulated using HP-advanced design system and load-pull technique. The simulation showed that a load mismatch of VSWR 3:1 can produce 10 dB attenuation in output power, relative to the power that would be the power that would be generated if there were no load mismatch.",

author = "\{De Lima\}, \{R. N.\} and B. Huyart and E. Bergeault and L. Jallet",

year = "2000",

month = aug,

day = "3",

doi = "10.1049/el:20000955",

language = "English",

volume = "36",

pages = "1393--1394",

journal = "Electronics Letters",

issn = "0013-5194",

number = "16",

}

TY - JOUR

T1 - MMIC impedance matching system

AU - De Lima, R. N.

AU - Huyart, B.

AU - Bergeault, E.

AU - Jallet, L.

PY - 2000/8/3

Y1 - 2000/8/3

N2 - An MMIC impedance system incorporating an on-chip load reflection-coefficient measurement system is presented. The system is capable of correcting load mismatches of up to 5:1 better than 2:1 VSWR with an insertion loss between 3.5-5.8 dB. A SiGe power amplifier, with reactive tee input-output matching circuits, was simulated using HP-advanced design system and load-pull technique. The simulation showed that a load mismatch of VSWR 3:1 can produce 10 dB attenuation in output power, relative to the power that would be the power that would be generated if there were no load mismatch.

AB - An MMIC impedance system incorporating an on-chip load reflection-coefficient measurement system is presented. The system is capable of correcting load mismatches of up to 5:1 better than 2:1 VSWR with an insertion loss between 3.5-5.8 dB. A SiGe power amplifier, with reactive tee input-output matching circuits, was simulated using HP-advanced design system and load-pull technique. The simulation showed that a load mismatch of VSWR 3:1 can produce 10 dB attenuation in output power, relative to the power that would be the power that would be generated if there were no load mismatch.

U2 - 10.1049/el:20000955

DO - 10.1049/el:20000955

M3 - Article

AN - SCOPUS:0034246098

SN - 0013-5194

VL - 36

SP - 1393

EP - 1394

JO - Electronics Letters

JF - Electronics Letters

IS - 16

ER -

MMIC impedance matching system

Résumé

Accès au document

Empreinte digitale

Contient cette citation