Multi-objective Optimisation of RISC-V CV32A6 for ML application

RISC-V architectures are rapidly gaining in popularity in embedded systems, in which each mW counts. Since AI-related applications such as image recognition or neural networks tend to be highly energy consuming, low-power techniques are required to optimise the autonomy of systems using SoCs to run such applications. However, the trade-off between energy consumption, application performance and resource use requires a multi-objective optimisation with a potentially very important number of optimisation parameters to be performed on the SoC. As they rely on heuristics that are likely to only return locally optimal solutions, empirical methods must be excluded. To address this issue, a technology-agnostic mathematical model is introduced to represent how optimisations are applied to a SoC, and a workflow designed to perform an intelligent exhaustive exploration of the optimisation space has been developed to highlight a subset of optimal processor configurations. Optimisation of the ARIANE/CV32A6 RISC-V processor, running a CNN propagation on a Xilinx Zynq 7020 FPGA, has shown very encouraging results using low degree configurations, and is likely to perform even better with higher degree configurations.