TY - GEN
T1 - Mutation of Formally Verified SysML Models
AU - Apvrille, Ludovic
AU - Sultan, Bastien
AU - Hotescu, Oana
AU - de Saqui-Sannes, Pierre
AU - Coudert, Sophie
N1 - Publisher Copyright:
© 2023 by SCITEPRESS - Science and Technology Publications, Lda.
PY - 2023/1/1
Y1 - 2023/1/1
N2 - Model checking of SysML models contributes to detect design errors and to check design decisions against user requirements. Yet, each time a model is modified, formal verification must be performed again, which makes model evolution costly and hampers the use of agile development methods. Based on former contributions on dependency graphs, the paper proposes to facilitate updates (also called mutations) on models: whenever a mutation is performed on a model, the algorithms introduced in this paper can determine which proofs remain valid and which ones must be performed again. The main idea to reduce the proof obligation is to identify new paths that need to be re-verified. Our algorithm reuses the results of previous proofs as much as possible in order to lower the complexity of the proof. The paper focuses on reachability proofs. A real-time communication architecture based on TSN (Time Sensitive Networking) illustrates the approach and performance results are presented.
AB - Model checking of SysML models contributes to detect design errors and to check design decisions against user requirements. Yet, each time a model is modified, formal verification must be performed again, which makes model evolution costly and hampers the use of agile development methods. Based on former contributions on dependency graphs, the paper proposes to facilitate updates (also called mutations) on models: whenever a mutation is performed on a model, the algorithms introduced in this paper can determine which proofs remain valid and which ones must be performed again. The main idea to reduce the proof obligation is to identify new paths that need to be re-verified. Our algorithm reuses the results of previous proofs as much as possible in order to lower the complexity of the proof. The paper focuses on reachability proofs. A real-time communication architecture based on TSN (Time Sensitive Networking) illustrates the approach and performance results are presented.
KW - Model Checking
KW - Model Mutation
KW - SysML
KW - Time Sensitive Network
UR - https://www.scopus.com/pages/publications/105001870383
U2 - 10.5220/0011648300003402
DO - 10.5220/0011648300003402
M3 - Conference contribution
AN - SCOPUS:105001870383
SN - 9789897586330
T3 - International Conference on Model-Driven Engineering and Software Development
SP - 31
EP - 42
BT - Proceedings of the 11th International Conference on Model-Based Software and Systems Engineering
A2 - Domínguez Mayo, Francisco José
A2 - Pires, Luís Ferreira
A2 - Seidewitz, Edwin
PB - Science and Technology Publications, Lda
T2 - 11th International Conference on Model-Based Software and Systems Engineering, MODELSWARD 2023
Y2 - 19 February 2023 through 21 February 2023
ER -