TY - GEN
T1 - NOC based MPSOC directory based cache coherency with OCP-IP protocol
AU - Hammami, Omar
AU - Li, Xinyu
PY - 2013/12/1
Y1 - 2013/12/1
N2 - Rapid advances of silicon and parallel processing technologies allow the building of multiprocessor systems-on-chip (MPSoCs). Cache coherency problem becomes one of the major design issues to improve the performance of multiprocessor. We first realize a directory based cache coherency scheme of Network on Chip (NoC) based MPSOC implemented on FPGA using the industrial standard protocol of OCP-IP. In this paper we present the system architecture and implementation results which shows that NoC based coherency system is well scalable. JTAG and PCI based debug system are developed for visualizing the application execution of our NoC based MPSoC cache coherency system.
AB - Rapid advances of silicon and parallel processing technologies allow the building of multiprocessor systems-on-chip (MPSoCs). Cache coherency problem becomes one of the major design issues to improve the performance of multiprocessor. We first realize a directory based cache coherency scheme of Network on Chip (NoC) based MPSOC implemented on FPGA using the industrial standard protocol of OCP-IP. In this paper we present the system architecture and implementation results which shows that NoC based coherency system is well scalable. JTAG and PCI based debug system are developed for visualizing the application execution of our NoC based MPSoC cache coherency system.
UR - https://www.scopus.com/pages/publications/84894437485
U2 - 10.1109/IDT.2013.6727139
DO - 10.1109/IDT.2013.6727139
M3 - Conference contribution
AN - SCOPUS:84894437485
SN - 9781479935253
T3 - 2013 8th IEEE Design and Test Symposium, IDT 2013
BT - 2013 8th IEEE Design and Test Symposium, IDT 2013
T2 - 2013 8th IEEE Design and Test Symposium, IDT 2013
Y2 - 16 December 2013 through 18 December 2013
ER -