TY - GEN
T1 - Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core
AU - Cai, Hao
AU - Wang, You
AU - Naviner, Lirida
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/20
Y1 - 2017/7/20
N2 - In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account sensing delay, dynamic power, leakage power and process variations. Results show that the transmission gate pulsed latch (TGPL) based NVFF exhibits enhanced performance compared to conventional master-slave structure, with improved variability, 15.7% fast timing metric, 76% dynamic, 79% leakage power reduction and 30% layout area reduction in multi-bit NV-FF hybrid circuit integration. The pulsed latch FF core can enhance NVFF scalability with increased energy-delay and layout efficiency, as well as reduced active and leakage energy.
AB - In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account sensing delay, dynamic power, leakage power and process variations. Results show that the transmission gate pulsed latch (TGPL) based NVFF exhibits enhanced performance compared to conventional master-slave structure, with improved variability, 15.7% fast timing metric, 76% dynamic, 79% leakage power reduction and 30% layout area reduction in multi-bit NV-FF hybrid circuit integration. The pulsed latch FF core can enhance NVFF scalability with increased energy-delay and layout efficiency, as well as reduced active and leakage energy.
KW - FDSOI
KW - leakage reduction
KW - low power
KW - magnetic tunnel junction
KW - non-volatile flip-flops
UR - https://www.scopus.com/pages/publications/85027254262
U2 - 10.1109/ISVLSI.2017.19
DO - 10.1109/ISVLSI.2017.19
M3 - Conference contribution
AN - SCOPUS:85027254262
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 57
EP - 61
BT - Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
A2 - Reis, Ricardo
A2 - Stan, Mircea
A2 - Huebner, Michael
A2 - Voros, Nikolaos
PB - IEEE Computer Society
T2 - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Y2 - 3 July 2017 through 5 July 2017
ER -