Optimum LDPC decoder: A memory architecture problem

Erick Amador; Renaud Pacalet; Vincent Rezard

Optimum LDPC decoder: A memory architecture problem

Erick Amador
, Renaud Pacalet
, Vincent Rezard

Eurecom
Infineon Technologies France

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

Résumé

This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.

langue originale	Anglais
titre	2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Pages	891-896
Nombre de pages	6
état	Publié - 10 nov. 2009
Evénement	2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, États-Unis Durée: 26 juil. 2009 → 31 juil. 2009

Série de publications

Nom	Proceedings - Design Automation Conference
ISSN (imprimé)	0738-100X

Une conférence

Une conférence	2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Pays/Territoire	États-Unis
La ville	San Francisco, CA
période	26/07/09 → 31/07/09

SDG des Nations Unies

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title = "Optimum LDPC decoder: A memory architecture problem",

abstract = "This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.",

keywords = "LDPC codes, Low power architectures, Memory optimization",

author = "Erick Amador and Renaud Pacalet and Vincent Rezard",

year = "2009",

month = nov,

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series = "Proceedings - Design Automation Conference",

pages = "891--896",

booktitle = "2009 46th ACM/IEEE Design Automation Conference, DAC 2009",

note = "2009 46th ACM/IEEE Design Automation Conference, DAC 2009 ; Conference date: 26-07-2009 Through 31-07-2009",

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Optimum LDPC decoder: A memory architecture problem. / Amador, Erick; Pacalet, Renaud; Rezard, Vincent.
2009 46th ACM/IEEE Design Automation Conference, DAC 2009. 2009. p. 891-896 5227131 (Proceedings - Design Automation Conference).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

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N2 - This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.

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KW - LDPC codes

KW - Low power architectures

KW - Memory optimization

M3 - Conference contribution

AN - SCOPUS:70350731282

SN - 9781605584973

T3 - Proceedings - Design Automation Conference

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BT - 2009 46th ACM/IEEE Design Automation Conference, DAC 2009

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Optimum LDPC decoder: A memory architecture problem

Résumé

Série de publications

Une conférence

SDG des Nations Unies

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Contient cette citation