Physical design of FPGA interconnect to prevent information leakage

Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin

doi:10.1007/978-3-540-78610-8_11

Physical design of FPGA interconnect to prevent information leakage

Sumanta Chaudhuri
, Sylvain Guilley
, Philippe Hoogvorst
, Jean Luc Danger
, Taha Beyrouthy
, Alin Razafindraibe
, Laurent Fesquet
, Marc Renaudin

CNRS
TIMA Laboratory, Institut National Polytechnique de Grenoble

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

Résumé

In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

langue originale	Anglais
titre	Reconfigurable Computing
Sous-titre	Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings
Pages	87-98
Nombre de pages	12
Les DOIs	https://doi.org/10.1007/978-3-540-78610-8_11
état	Publié - 22 sept. 2008
Evénement	4th International Workshop on Applied Reconfigurable Computing, ARC 2008 - London, Royaume-Uni Durée: 26 mars 2008 → 28 mars 2008

Série de publications

Nom	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	4943 LNCS
ISSN (imprimé)	0302-9743
ISSN (Electronique)	1611-3349

Une conférence

Une conférence	4th International Workshop on Applied Reconfigurable Computing, ARC 2008
Pays/Territoire	Royaume-Uni
La ville	London
période	26/03/08 → 28/03/08

Accès au document

10.1007/978-3-540-78610-8_11

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Lien vers la publication dans Scopus

Contient cette citation

Chaudhuri, S., Guilley, S., Hoogvorst, P., Danger, J. L., Beyrouthy, T., Razafindraibe, A., Fesquet, L., & Renaudin, M. (2008). Physical design of FPGA interconnect to prevent information leakage. Dans Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings (p. 87-98). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol 4943 LNCS). https://doi.org/10.1007/978-3-540-78610-8_11

Chaudhuri, Sumanta ; Guilley, Sylvain ; Hoogvorst, Philippe et al. / Physical design of FPGA interconnect to prevent information leakage. Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. 2008. p. 87-98 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{ff1ce4aa43ed456d89a15f696de50cac,

title = "Physical design of FPGA interconnect to prevent information leakage",

abstract = "In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn \& Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.",

author = "Sumanta Chaudhuri and Sylvain Guilley and Philippe Hoogvorst and Danger, \{Jean Luc\} and Taha Beyrouthy and Alin Razafindraibe and Laurent Fesquet and Marc Renaudin",

year = "2008",

month = sep,

day = "22",

doi = "10.1007/978-3-540-78610-8\_11",

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series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

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Chaudhuri, S, Guilley, S, Hoogvorst, P, Danger, JL, Beyrouthy, T, Razafindraibe, A, Fesquet, L & Renaudin, M 2008, Physical design of FPGA interconnect to prevent information leakage. Dans Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOL. 4943 LNCS, p. 87-98, 4th International Workshop on Applied Reconfigurable Computing, ARC 2008, London, Royaume-Uni, 26/03/08. https://doi.org/10.1007/978-3-540-78610-8_11

Physical design of FPGA interconnect to prevent information leakage. / Chaudhuri, Sumanta; Guilley, Sylvain; Hoogvorst, Philippe et al.
Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. 2008. p. 87-98 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol 4943 LNCS).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

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AU - Chaudhuri, Sumanta

AU - Guilley, Sylvain

AU - Hoogvorst, Philippe

AU - Danger, Jean Luc

AU - Beyrouthy, Taha

AU - Razafindraibe, Alin

AU - Fesquet, Laurent

AU - Renaudin, Marc

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N2 - In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

AB - In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

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Chaudhuri S, Guilley S, Hoogvorst P, Danger JL, Beyrouthy T, Razafindraibe A et al. Physical design of FPGA interconnect to prevent information leakage. Dans Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. 2008. p. 87-98. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-78610-8_11

Physical design of FPGA interconnect to prevent information leakage

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