Practical metrics for evaluation of fault-tolerant logic design

Paper presents a technology-independent metric for evaluation of logical masking properties of logic circuits and method for accurate reliability comparison of fault-tolerant logic designs. Proposed metric is based on the observability computation, providing certain trade-off between computational complexity and accuracy, reducing exponential complexity with regard to the number of elements to the linear relationship. It is based on evaluation of upper and lower bounds for the error polynomial based on the observability of gates. Simulation results of comparison with well-known observability-based method are presented for applications on the LGSynth91 and ISCAS85 benchmark circuits. It is shown that the proposed approach provides results that are more accurate on the most of the benchmark circuits while maintaining the same computational complexity. The approach for calculation of upper and lower bounds for observability-based method was generalized for multiple failures and arbitrary number of simulations. This approach has been applied to the problem of accurate reliability comparison of logic circuits, significantly reducing the number of simulations required to get an unambiguous solution.