Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI

Francisco Veirano; Lirida Naviner; Fernando Silveira

doi:10.1109/PATMOS.2016.7833694

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI

Francisco Veirano
, Lirida Naviner
, Fernando Silveira

Instituto de Ingeniería Eléctrica
Universidad de la República
Université Paris-Saclay

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

3 Citations (Scopus)

Résumé

In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB biasing scheme, simulations show that around 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.

langue originale	Anglais
titre	Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Editeur	Institute of Electrical and Electronics Engineers Inc.
Pages	243-249
Nombre de pages	7
ISBN (Electronique)	9781509007332
Les DOIs	https://doi.org/10.1109/PATMOS.2016.7833694
état	Publié - 25 janv. 2017
Modification externe	Oui
Evénement	26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 - Bremen, Allemagne Durée: 21 sept. 2016 → 23 sept. 2016

Série de publications

Nom	Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016

Une conférence

Une conférence	26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Pays/Territoire	Allemagne
La ville	Bremen
période	21/09/16 → 23/09/16

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10.1109/PATMOS.2016.7833694

Contient cette citation

Veirano, F., Naviner, L., & Silveira, F. (2017). Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. Dans Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 (p. 243-249). Article 7833694 (Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PATMOS.2016.7833694

Veirano, Francisco ; Naviner, Lirida ; Silveira, Fernando. / Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 243-249 (Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016).

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abstract = "In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB biasing scheme, simulations show that around 30\% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.",

author = "Francisco Veirano and Lirida Naviner and Fernando Silveira",

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doi = "10.1109/PATMOS.2016.7833694",

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Veirano, F, Naviner, L & Silveira, F 2017, Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. Dans Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016., 7833694, Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Institute of Electrical and Electronics Engineers Inc., p. 243-249, 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Allemagne, 21/09/16. https://doi.org/10.1109/PATMOS.2016.7833694

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. / Veirano, Francisco; Naviner, Lirida; Silveira, Fernando.
Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 243-249 7833694 (Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

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AU - Naviner, Lirida

AU - Silveira, Fernando

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N2 - In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB biasing scheme, simulations show that around 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.

AB - In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB biasing scheme, simulations show that around 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.

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Veirano F, Naviner L, Silveira F. Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. Dans Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 243-249. 7833694. (Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016). doi: 10.1109/PATMOS.2016.7833694

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI

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