Reconfigurable implementation issues of a detection scheme for DS-CDMA high data rate connections

In this paper a reconfigurable implementation for the data detection in high data rate direct sequence code division multiple access (DS-CDMA) connections is presented. Due to some well defined real time system parameters, traditional implementations of this detector which deal with the mean operational case are not optimal. They consume a lot of power in the favorable operational cases and they loose a diversity gain in the worst cases. Thanks to reconfigurability, a detector can adapt its configuration to each operational condition. Reconfigurability can perform jointly performance and computational power optimization. Implementation issues have shown that the traditional DSPs provide a high degree of flexibility but they are inefficient for the high rate processing constraints involved to DS-CDMA detection with low spreading factors (SF). A reconfigurable hardware implementation is proposed and analyzed which besides its performance capabilities provides a minimum area overhead.