Regular 2D NASIC-based architecture and design space exploration

Ciprian Teodorov; Pritish Narayanan; Loic Lagadec; Catherine Dezan

doi:10.1109/NANOARCH.2011.5941486

Regular 2D NASIC-based architecture and design space exploration

Ciprian Teodorov
, Pritish Narayanan
, Loic Lagadec
, Catherine Dezan

ENSTA

University of Massachusetts
Université de Brest (UBO)

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

10 Citations (Scopus)

Résumé

As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.

langue originale	Anglais
titre	Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
Pages	70-77
Nombre de pages	8
Les DOIs	https://doi.org/10.1109/NANOARCH.2011.5941486
état	Publié - 11 août 2011
Evénement	2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 - San Diego, CA, États-Unis Durée: 8 juin 2011 → 9 juin 2011

Série de publications

Nom	Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Une conférence

Une conférence	2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
Pays/Territoire	États-Unis
La ville	San Diego, CA
période	8/06/11 → 9/06/11

Accès au document

10.1109/NANOARCH.2011.5941486

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Contient cette citation

Teodorov, C., Narayanan, P., Lagadec, L., & Dezan, C. (2011). Regular 2D NASIC-based architecture and design space exploration. Dans Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 (p. 70-77). Article 5941486 (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011). https://doi.org/10.1109/NANOARCH.2011.5941486

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title = "Regular 2D NASIC-based architecture and design space exploration",

abstract = "As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.",

author = "Ciprian Teodorov and Pritish Narayanan and Loic Lagadec and Catherine Dezan",

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note = "2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 ; Conference date: 08-06-2011 Through 09-06-2011",

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Teodorov, C, Narayanan, P, Lagadec, L & Dezan, C 2011, Regular 2D NASIC-based architecture and design space exploration. Dans Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011., 5941486, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, p. 70-77, 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, États-Unis, 8/06/11. https://doi.org/10.1109/NANOARCH.2011.5941486

Regular 2D NASIC-based architecture and design space exploration. / Teodorov, Ciprian; Narayanan, Pritish; Lagadec, Loic et al.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 70-77 5941486 (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

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N2 - As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.

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Teodorov C, Narayanan P, Lagadec L, Dezan C. Regular 2D NASIC-based architecture and design space exploration. Dans Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 70-77. 5941486. (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011). doi: 10.1109/NANOARCH.2011.5941486

Regular 2D NASIC-based architecture and design space exploration

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Une conférence

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