TY - GEN
T1 - Reliability analysis of combinational circuits based on a probabilistic binomial model
AU - De Vasconcelos, Maí C.R.
AU - Franco, Denis T.
AU - Naviner, Lirida A.De B.
AU - Naviner, Jean François
PY - 2008/9/30
Y1 - 2008/9/30
N2 - Reliability analysis of digital circuits is becoming an important feature in the design process of nanoscale systems. Understanding the relations between circuit structure and its reliability allows the designer to implement some tradeoffs that can improve the resulting design. This work presents a probabilistic model that computes the reliability of combinational logic circuits relating to single and multiple faults. The methodology is targeted (but not limited) to circuits generated by synthesis tools, and standard cell based implementation. To validate the proposed methodology we have studied the reliability of some adder structures. Complexity and scalability of the model are discussed and some optimizations are presented.
AB - Reliability analysis of digital circuits is becoming an important feature in the design process of nanoscale systems. Understanding the relations between circuit structure and its reliability allows the designer to implement some tradeoffs that can improve the resulting design. This work presents a probabilistic model that computes the reliability of combinational logic circuits relating to single and multiple faults. The methodology is targeted (but not limited) to circuits generated by synthesis tools, and standard cell based implementation. To validate the proposed methodology we have studied the reliability of some adder structures. Complexity and scalability of the model are discussed and some optimizations are presented.
U2 - 10.1109/NEWCAS.2008.4606383
DO - 10.1109/NEWCAS.2008.4606383
M3 - Conference contribution
AN - SCOPUS:52449091594
SN - 9781424423323
T3 - 2008 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA
SP - 310
EP - 313
BT - 2008 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA
T2 - 2008 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA
Y2 - 22 June 2008 through 25 June 2008
ER -