TY - GEN
T1 - Reliability analysis of combinational circuits with the influences of noise and single-event transients
AU - Liu, Kaikai
AU - Cai, Hao
AU - An, Ting
AU - Naviner, Lirida
AU - Naviner, Jean Francois
AU - Petit, Herve
PY - 2013/12/1
Y1 - 2013/12/1
N2 - Noise-immunity is an important design criterion with CMOS dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints.
AB - Noise-immunity is an important design criterion with CMOS dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints.
UR - https://www.scopus.com/pages/publications/84891280263
U2 - 10.1109/DFT.2013.6653609
DO - 10.1109/DFT.2013.6653609
M3 - Conference contribution
AN - SCOPUS:84891280263
SN - 9781479915835
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SP - 218
EP - 223
BT - Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013
T2 - 2013 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013
Y2 - 2 October 2013 through 4 October 2013
ER -