Separating control and data processing in RT level virtual IP components

SoC validation has become more challenging due to extensive reuse of Intellectual Property (IP) components in today's design. Simulation and Formal validation techniques are suffering longer computation time, limited coverage and combinatorial explosion. To enhance both techniques, it is necessary to work at high abstraction level. In this perspective, the proposed methodology assists abstraction of IP components. We present in this paper a technique to separate control state machine from the data processing in Register Transfer Level (RTL) IP models as first requirement for our notion of abstract data processing. A dependency analysis is performed on the given model based on the information of control and data inputs provided by the designer to obtain two separate entities in the form of control and data slice. The control slice and abstract functional representation of data slice are intended to be used for rapid simulation, static formal analysis and understanding the functionality of the model.