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Shadow-scan design with low latency overhead and in-situ slack-time monitoring

  • CEA/UVSQ/CNRS
  • Univ. Joseph Fourier-Grenoble 1

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collectionContribution à une conférenceRevue par des pairs

1 Citation (Scopus)

Résumé

Shadow-scan solutions are proposed in order to facilitate the implementation of faster scan flip-flops (FFs) with optional support for in-situ slack-time monitoring. These solutions can be applied to system FFs placed at the end of timing-critical paths while standard-scan cells are deployed in the rest of the system. Automated scan stitching and automated test pattern generation (ATPG) can be performed transparently with commercial tools. The generated test patterns cover not only the mission logic but also the monitoring infrastructure. The latency of itc'99 benchmark circuits could be reduced with up to 10% while the stuck-at fault coverage (FC) was preserved as compared to circuit versions with full standard-scan design. Limited variations in the number of test patterns were observed when support for in-situ slack-time monitoring was provided.

langue originaleAnglais
titreProceedings - 2014 19th IEEE European Test Symposium, ETS 2014
EditeurIEEE Computer Society
ISBN (imprimé)9781479934157
Les DOIs
étatPublié - 1 janv. 2014
Evénement19th IEEE European Test Symposium, ETS 2014 - Paderborn, Allemagne
Durée: 26 mai 201430 mai 2014

Série de publications

NomProceedings - 2014 19th IEEE European Test Symposium, ETS 2014

Une conférence

Une conférence19th IEEE European Test Symposium, ETS 2014
Pays/TerritoireAllemagne
La villePaderborn
période26/05/1430/05/14

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