Silicon-level solutions to counteract passive and active attacks

Sylvain Guilley; Laurent Sauvage; Jean Luc Danger; Nidhal Selmane; Renaud Pacalet

doi:10.1109/FDTC.2008.18

Silicon-level solutions to counteract passive and active attacks

Sylvain Guilley
, Laurent Sauvage
, Jean Luc Danger
, Nidhal Selmane
, Renaud Pacalet

Telecom Paris

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

Résumé

This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics. The purpose of these prototype circuits is to experience with the published "implementation-level" attacks (SPA, DPA, EMA, templates, DFA). We report our conclusions about the practicability of these attacks: which ones are the most simple to mount, and which ones require more skill, time, equipments, etc. The potential of FPGAs as security evaluation commodities at design time is also detailed. Then, we discuss about "dual counter-measures", that are meant to resist both passive and active attacks. This study started four years ago with TIMA (Grenoble), in the framework of the project MARS [31]. We highlight some research directions towards dependable and cost-effective dual counter-measures.

langue originale	Anglais
titre	Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008
Pages	3-17
Nombre de pages	15
Les DOIs	https://doi.org/10.1109/FDTC.2008.18
état	Publié - 6 oct. 2008
Evénement	5th International Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2008 - Washington, DC, États-Unis Durée: 10 août 2008 → 10 août 2008

Série de publications

Nom	Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008

Une conférence

Une conférence	5th International Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2008
Pays/Territoire	États-Unis
La ville	Washington, DC
période	10/08/08 → 10/08/08

Accès au document

10.1109/FDTC.2008.18

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Lien vers la publication dans Scopus

Contient cette citation

Guilley, S., Sauvage, L., Danger, J. L., Selmane, N., & Pacalet, R. (2008). Silicon-level solutions to counteract passive and active attacks. Dans Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008 (p. 3-17). Article 4599552 (Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008). https://doi.org/10.1109/FDTC.2008.18

@inproceedings{bb4fe3e790a940809af74aa00d3b94bd,

title = "Silicon-level solutions to counteract passive and active attacks",

abstract = "This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics. The purpose of these prototype circuits is to experience with the published {"}implementation-level{"} attacks (SPA, DPA, EMA, templates, DFA). We report our conclusions about the practicability of these attacks: which ones are the most simple to mount, and which ones require more skill, time, equipments, etc. The potential of FPGAs as security evaluation commodities at design time is also detailed. Then, we discuss about {"}dual counter-measures{"}, that are meant to resist both passive and active attacks. This study started four years ago with TIMA (Grenoble), in the framework of the project MARS [31]. We highlight some research directions towards dependable and cost-effective dual counter-measures.",

keywords = "Attacks mitigation techniques, Differential fault attack (DFA), Differential power analysis (DPA), Dual-rail with precharge logic (DPL), FPGA as evaluation platforms, SecLib DPL style, SecMat ASIC family, Side-channel attacks (SCA)",

author = "Sylvain Guilley and Laurent Sauvage and Danger, \{Jean Luc\} and Nidhal Selmane and Renaud Pacalet",

year = "2008",

month = oct,

day = "6",

doi = "10.1109/FDTC.2008.18",

language = "English",

isbn = "9780769533148",

series = "Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008",

pages = "3--17",

booktitle = "Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008",

note = "5th International Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2008 ; Conference date: 10-08-2008 Through 10-08-2008",

}

Guilley, S, Sauvage, L, Danger, JL, Selmane, N & Pacalet, R 2008, Silicon-level solutions to counteract passive and active attacks. Dans Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008., 4599552, Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008, p. 3-17, 5th International Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2008, Washington, DC, États-Unis, 10/08/08. https://doi.org/10.1109/FDTC.2008.18

Silicon-level solutions to counteract passive and active attacks. / Guilley, Sylvain; Sauvage, Laurent; Danger, Jean Luc et al.
Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008. 2008. p. 3-17 4599552 (Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008).

Résultats de recherche: Le chapitre dans un livre, un rapport, une anthologie ou une collection › Contribution à une conférence › Revue par des pairs

TY - GEN

T1 - Silicon-level solutions to counteract passive and active attacks

AU - Guilley, Sylvain

AU - Sauvage, Laurent

AU - Danger, Jean Luc

AU - Selmane, Nidhal

AU - Pacalet, Renaud

PY - 2008/10/6

Y1 - 2008/10/6

N2 - This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics. The purpose of these prototype circuits is to experience with the published "implementation-level" attacks (SPA, DPA, EMA, templates, DFA). We report our conclusions about the practicability of these attacks: which ones are the most simple to mount, and which ones require more skill, time, equipments, etc. The potential of FPGAs as security evaluation commodities at design time is also detailed. Then, we discuss about "dual counter-measures", that are meant to resist both passive and active attacks. This study started four years ago with TIMA (Grenoble), in the framework of the project MARS [31]. We highlight some research directions towards dependable and cost-effective dual counter-measures.

AB - This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics. The purpose of these prototype circuits is to experience with the published "implementation-level" attacks (SPA, DPA, EMA, templates, DFA). We report our conclusions about the practicability of these attacks: which ones are the most simple to mount, and which ones require more skill, time, equipments, etc. The potential of FPGAs as security evaluation commodities at design time is also detailed. Then, we discuss about "dual counter-measures", that are meant to resist both passive and active attacks. This study started four years ago with TIMA (Grenoble), in the framework of the project MARS [31]. We highlight some research directions towards dependable and cost-effective dual counter-measures.

KW - Attacks mitigation techniques

KW - Differential fault attack (DFA)

KW - Differential power analysis (DPA)

KW - Dual-rail with precharge logic (DPL)

KW - FPGA as evaluation platforms

KW - SecLib DPL style

KW - SecMat ASIC family

KW - Side-channel attacks (SCA)

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DO - 10.1109/FDTC.2008.18

M3 - Conference contribution

AN - SCOPUS:52949101402

SN - 9780769533148

T3 - Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008

SP - 3

EP - 17

BT - Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008

T2 - 5th International Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2008

Y2 - 10 August 2008 through 10 August 2008

ER -

Guilley S, Sauvage L, Danger JL, Selmane N, Pacalet R. Silicon-level solutions to counteract passive and active attacks. Dans Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008. 2008. p. 3-17. 4599552. (Fault Diagnosis and Tolerance in Cryptography - Proceedings of the 5th International Workshop, FDTC 2008). doi: 10.1109/FDTC.2008.18

Silicon-level solutions to counteract passive and active attacks

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